library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity	tx_mux is
	port( clk_100m:	     in std_logic;
		  da,db,dc,dd:   in std_logic_vector(7 downto 0);
		  de,df,dg,dh:   in std_logic_vector(7 downto 0);
		  clk_12m,sel:   out std_logic;
		  ld:	           out std_logic;---not cy125mo	 
	      dout:          out std_logic_vector(17 downto 0);
	      led:           out std_logic_vector(15 downto 0);
	      clk_6m:        out std_logic
		);
end entity;
architecture be of tx_mux is
signal cn,fas:	           std_logic_vector(7 downto 0);
signal clk25m:	           std_logic;
signal daa,dbb,dcc,ddd:	   std_logic_vector(7 downto 0);
signal dee,dff,dgg,dhh:	   std_logic_vector(7 downto 0);
begin
    fas<="11011001";   clk_6m<=cn(3);
	clk_12m<=not cn(2);
	sel<=cn(2);
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   cn<=cn+1;
		   if conv_integer(cn(1 downto 0))=0 then
		      dout(7 downto 0)<=daa;
		      dout(15 downto 8)<=dee;		      
		   elsif conv_integer(cn(1 downto 0))=1 then
		      dout(7 downto 0)<=dbb;
		      dout(15 downto 8)<=dff;
		   elsif conv_integer(cn(1 downto 0))=2 then
		      dout(7 downto 0)<=dcc;
		      dout(15 downto 8)<=dgg;
		   elsif conv_integer(cn(1 downto 0))=3 then
			  dout(7 downto 0)<=ddd;
		      dout(15 downto 8)<=dhh;
		   end if;
		   if conv_integer(cn(7 downto 0))<8 then
		      dout(16)<=fas(conv_integer(cn(7 downto 0)));
		   else
		      dout(16)<='1';
		   end if;		   
		   dout(17)<='1';			
		end if;		
	end process;
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   if conv_integer(cn(1 downto 0))=3 then
		      daa<=da;    dbb<=db;   dcc<=dc;   ddd<=dd;
		      dee<=de;    dff<=df;   dgg<=dg;   dhh<=dh;
		   end if;
		   if conv_integer(cn(7 downto 0))=255 then
		      ld<='0';
		   else
		      ld<='1';
		   end if;
		end if;
	end process;
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   if conv_integer(cn(2 downto 0))=2 then
		      led(0)<=not daa(7);
		      led(2)<=not dbb(7);
		      led(4)<=not dcc(7);
		      led(6)<=not ddd(7);
		      led(8)<=not dee(7);
		      led(10)<=not dff(7);
		      led(12)<=not dgg(7);
		      led(14)<=not dhh(7);
		   elsif conv_integer(cn(2 downto 0))=6 then
		      led(1)<=not daa(7);
		      led(3)<=not dbb(7);
		      led(5)<=not dcc(7);
		      led(7)<=not ddd(7);
		      led(9)<=not dee(7);
		      led(11)<=not dff(7);
		      led(13)<=not dgg(7);
		      led(15)<=not dhh(7);		     
		   end if;
		end if;
	end process;		
end be;
